Industry leader is looking for a Design Verification Engineer who will join a team of experienced network switching design engineers developing and supporting the most advanced technology in the enterprise network chip industry. This is a full time position in San Jose, California.
Qualifications:
BSEE required/MSEE preferred plus minimum 7 years of experience in networking ASIC verification.
Working knowledge is required in the following areas:
RTL (front-end) design
VERA or System Verilog
Knowledge of C, TCL a plus
Ethernet, IEEE 802.1, IEEE 802.3
Excellent communication and presentation skills
Well organized, methodical, and detail oriented
Team player and easy to work with
Responsibilities:
The successful candidate will be working within an IP center of excellence group who is the focal center in providing this new technology to the company.
IC Design Verification of Ethernet packet pipeline which performs deep packet inspection, processing and statistics, packet modification, at 10Gbps and 40Gbps rates. Including link layer security protocols based on IEEE802.1AE, and AES-GCM algorithm
Creating, maintaining and supporting releases for top random and checker environments using high level verification language
Comprehensive benefits package and relocation assistance is available.
US Citizens and Green Card Holders and those authorized to work in the US are encouraged to apply. We are unable to sponsor H1b candidates at this time.
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