OBJECTIVE
To pursue a full-time full time position in Circuit Design or Circuit Verification/Test.
EXPERIENCE
1998 – present, Circuit Design Engineer
Projects:
Axcelerator --- Antifuse Technology
Designed FPGA Core Modules configurable to a variety of combinational and sequential logics including arithmetic modules. Performed the verification of the module functions using Verilog simulations. Developed the circuit optimization methodology (timing, area and power) using HSPICE simulations.
Designed the segmentable Global Networks with low power management. Performed the performance optimization using HSPICE simulation.
Designed the uProbe circuitry with single ended sense amplifier. Performed the performance optimization using HSPICE simulation.
Designed the Power–On-Reset circuitry with multiple power supplies. Performed the functional verification and performance optimization using HSPICE simulation.
Simulated multi-standard IO operations and full chip SSO using HSPICE and HSIM.
Evaluated full chip power grid (Electro-migration & IR drop) and performed full chip power consumption analysis using VoltageStorm.
RT- Axcelerator ---- Antifuse Technology
Designed Radiation-Hardened FPGA Core Modules with Single Event Upset (SEU) mitigations.
Designed Radiation-Hardened Global Networks with Single Event Transient (SET) mitigations.
Performed simulation of the charge pump operations and developed the performance enhancement methodology to 4-phase pump design.
DTRA ---- Flash Technology
Designed address decoders and high voltage drivers for flash memory Erase, Program, Read operations.
Designed Radiation-Hardened FPGA core modules with Single Event Transient (SET) and Single Event Upset (SEU) mitigations.
Designed Radiation-Hardened Global Networks with Single Event Transient (SET) mitigation.
Designed the core modules test circuitry with observability and controllability through JTAG and uP8051 interfaces.
Performed the simulation of DAC operations.
RIO, Misc. projects ---- SRAM Technology
Performed the simulation of 5T-SRAM Array clear, write, read operations using HSPICE.
Performed the verification of peripheral circuitry logic include address decoders, counters, etc. using Verilog.
Performed the simulation of USRAM FIFO operations using HSIM.
Designed LVTTL IO modules using cascode structure.
Reverse engineering (tracing layout to generate schematics) on several PLL designs, and performed the simulations of PLL operations.
SKILLS
- CAD Tools:
Proficient in Cadence Opus, ViewLogic, ModelSim.
- Design Tools Language:
Proficient in HSPICE, HSIM, Verilog.
- Computer Programming Language:
Proficient C, BASIC, FORTRAN.
- OS and Computing Platforms:
Power user of UNIX and Windows.
EDUCATION
Ph.D. in Civil & Hydraulic Engineering, 1997
MS in Electrical Engineering, 1996
BS in Hydraulic Engineering, 1991
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